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MYSON TECHNOLOGY
FEATURES
* * * * *
MTV003N (MTV003)
Microprocessor Compatible Monitor Controller
Synchronous signal processing for use in green monitor applications. Easy command interface for external microprocessor controls. D/A converters up to 12V output. Built-in self-test pattern generator. On-chip clock oscillator allows external TTL level clock signal input.
GENERAL DESCRIPTION
MTV003 is intended for use in digital-controlled, power-conscious (Green) monitor applications. It integrates 4 major function blocks traditionally implemented in discrete parts and provides an easy interface for microprocessor controls. The functional blocks included in MTV003 are: SYNC processing, D/A converters, self-test pattern generator and command interface.
BLOCK DIAGRAM
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. MTV003 Revision 2.3 07/01/1998 1/13
MYSON TECHNOLOGY
1.0 CONNECTION DIAGRAM
(20 PIN PDIP 300 MIL PACKAGE)
MTV003N (MTV003)
2.0 PIN DESCRIPTIONS
Name VSS DA0 I/O O Pin# 1 2 Function Ground (0 V). Open-Drain PWM (Pulse Width Modulation) D/A Converter 0. The output pulse width is programmable by writing data to Reg10 with 8-bit resolution to control the pulse width duration from 0 to 255/256. The output frequency is 31.25KHz (or15.625KHz). In applications, the external pull-up resistor can be connected to 12V for the desired fullscale output. Open-Drain PWM D/A Converter 1. See DA0. The output pulse width is programmable by Reg11. Open-Drain PWM D/A Converter 2. See DA0. The output pulse width is programmable by Reg12. Horizontal Blank. The pulse width and the delay of HBLANK vs.HS input leading edges are programmable by Reg7 and Reg6, respectively. Vertical Blank. The output pulse width is programmable by Reg9. Crystal 1. Used to interface to the oscillator. An 8MHz(or 4MHz) crystal must be connected between this pin and pin X2. An appropriate capacitor to Ground, whose value depends on the specified CLof the crystal, must be connected. This pin can also be used as a direct input when the external oscillator is used.
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DA1 DA2 HBLANK
O O O
3 4 5
VBLANK X1
O I/O
6 7
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Name X2 I/O O Pin# 8
MTV003N (MTV003)
HS
I
9
VS
I
10
CMDB
I
11
DCK
I
12
DIO
I/O
13
STOUT
O
14
XDA4 XDA3 XDA2 XDA1 XDA0 VDD
O O O O O
15 16 17 18 19 20
Function Crystal 2. See X1. An appropriate capacitor to Ground, whose value depends on the specified CLof the crystal, must be connected. For the external clock source, this pin must be tied to Ground. Horizontal Sync. Horizontal synchronous signal input. The input level is TTL compatible with internal 0.2V hysteresis. An internal 50K Ohm pull-up resistor is connected to this pin. Vertical Sync. Vertical synchronous signal input. The input level is TTL compatible with internal 0.2V hysteresis. An internal 50K Ohm pull-up resistor is connected to this pin. Command Interface Enabler. A low active pin which must be forced to low in excess of 16 cycles of DCK for 1 successful access of command interface. It has an internal 50K Ohm pull-up resistor. Command Interface Clock. This pin is used as the timing base for command interface. The address or data portion for the serial in (out) of DIO is recognized by counting the number of DCKs. It has an internal 50K Ohm pull-up resistor. Command Interface Data. This pin is a bidirectional pin. A microprocessor can access any internal command registers through the protocol of the address portion followed by the succeeding data portion. It must complete 16 full DCK cycles for a valid access. Self-Test Video Output. (for self-test mode) This pin is the video output pin of the self-test pattern generator. The generator enabler, pattern modes, output band selection and output enabler are programmed by Reg16. CMOS PWM D/A Converter 4. See DA0. The output pulse width can be programmed by Reg30. It is a CMOS type output. CMOS PWM D/A Converter 3. See DA0. The output pulse width can be programmed by Reg29. It is a CMOS type output. CMOS PWM D/A Converter 2. See DA0. The output pulse width can be programmed by Reg28. It is a CMOS type output. CMOS PWM D/A Converter 1. See DA0. The output pulse width can be programmed by Reg27. It is a CMOS type output. CMOS PWM D/A Converter 0. See DA0. The output pulse width can be programmed by Reg26. It is a CMOS type output. Positive Power Supply. +5 volts. 2 decoupling capacitors, 0.1 uF and 100 uF, must be connected to VDD and Ground as close to the device as possible.
3.0 FUNCTIONAL DESCRIPTION
3.1 Crystal Oscillator and Clock Generator The crystal oscillator shall be connected to an 8MHz(or 4MHz) crystal. X1, as shown in Fig.1, can be used as an input source for the external clock or an output clock source to drive the external MCU. All timing specifications are based on the frequency of X1 (or X1 divided by 2). 3.2 PWM D/A Converter There are 2 types of D/A converters with 8-bit resolution: open-drain type (DA0 to DA2) and CMOS type (XDA0 to XDA4). The sampling frequency is 31.25KHz or 15.625KHz, depending on the use of the crystal. The maximum external voltage applied is 12V for the open-drain type, and the output pulse width is programmable
MTV003 Revision 2.3 07/01/1998 3/13
MYSON TECHNOLOGY
for each converter by setting the corresponding register. 3.3 SYNC Processor
MTV003N (MTV003)
The sync processor contains the following functions: polarity detection, presence detection, H-Freq counter, V-Freq counter and sync signal separation for input SYNC sources (HS and VS). It can be programmed to change the detected polarity status and output polarity of SYNC pins (HBLANK and VBLANK) by using the command interface. The timing diagrams of sync processing are shown as Fig. 2 in section 8.0. The internal SYNC signals (Hsync and Vsync) are extracted from different sources according to the following modes of operation. Mode Separate(H+V) Composite(H/V) Suspend Off VS present not present present not present HS present present not present not present Comment HS = H or H/V sync HS= H/V sync -
1 2 3 4
3.4 H-Freq Table After the "start H-Freq count" command is issued over 10 ms (for 15.7KHz) and HCFF(H-Freq Count Finished Flag) is set High, the H-Freq output (HF9 - HF0) is valid. The output value of H-Freq is calculated using the following formula: output value = [(1/fHfreq(KHz)) x 64 x 4000] / 16 H-Freq(KHz) 15.7 18.7 21.8 30 31.5 33.5 35.5 36.8 38 40 48 50 57 60 64 100 Output value hexadecimal 11 bits decimal 3FB 1019 357 855 2DD 733 215 533 1FB 507 1DD 477 1C2 450 1B2 434 1A5 421 190 400 14D 333 140 320 118 280 10A 266 0FA 250 0A0 160 Tolerance (%) 0.0981354 0.1169591 0.1364256 0.1876172 0.1972386 0.2096436 0.2222222 0.2304147 0.2375297 0.2500000 0.3003003 0.3125000 0.3571428 0.3759398 0.4000000 0.6250000
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3.5 V-Freq Table After the "start V-Freq count" command is issued over 120 ms (for 50HZ) and VCFF (V-Freq Count Finish Flag) is set High, the V-Freq output (VF8 - VF0) is valid. The output value of V-Freq is calculated according to the following formula: output value = [(4/fVfreq(Hz)) x 4000000] / (64 x 16)
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MYSON TECHNOLOGY
1 2 3 4 5 6 7 8 9 10 11 12 13 V-Freq(Hz) 20 56.25 59.94 60 60.32 60.53 66.67 70.069 70.08 72 72.378 72.7 87 Output value hexadecimal 9 bits decimal 30D 781 115 277 104 260 104 260 103 259 102 258 0EA 234 0DE 222 0DE 222 0D9 217 0D7 215 0D6 214 0B3 179
MTV003N (MTV003)
Tolerance (%) 0.12804 0.36101 0.38461 0.38461 0.38610 0.38759 0.42735 0.45045 0.45045 0.46082 0.46511 0.46728 0.55865
3.6 Command Interface The command interface contains 3 pins. Each transfer of command is comprised of 16 DCK clock periods. The first 8 DCK clocks are for the address and direction of DIO, and the succeeding 8 DCK clocks are for the data. Each transfer is initiated by setting CMDB Low. The CMDB pin must be pulled High after data transfer is completed. - Command Format B0 - 4 (ADD4 - 0) B5 (W/RB) B6 - 7 B8 - 15 (DA0 - 7) (DA7 - 0) - Register Allocation a. Read Transfer Address Portion ADD4-0 W/RB B0 - 4 B5 00000 0 00001 0 00010 0 00011 0 00100 0 Data Portion DA7 - 0 B11 B12
VSpre x HF4 x VF4 HVpre HCFF HF3 x VF3
: Address of the registers. : Transfer direction, 1=write, 0=read. : Reserved. : Data input when W/RB=1. Data output when W/RB=0.
Reg # Reg0 Reg1 Reg2 Reg3 Reg4
B8
Hpol x HF7 x VF7
B9
Vpol x HF6 x VF6
B10
HSpre x HF5 x VF5
B13
Hsl HF10 HF2 x VF2
B14
Vsl HF9 HF1 VCFF VF1
B15
x HF8 HF0 VF8 VF0
Table 4 b. Write Transfer Address Portion ADD4-0 W/RB B0 - 4 B5 00000 1 00001 1 00010 1 00011 1 Data Portion DA0 - 7 B11 B12
x Hpf1 x x x VBpl x x
Reg # Reg0 Reg1 Reg2 Reg3
B8
x Vpf0 x CLK4M
B9
x Vpf1 x TEST
B10
x Hpf0 x x
B13
x HBpl x x
B14
x HVcvs x x
B15
x x x x
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MYSON TECHNOLOGY
Reg4 Reg5 Reg6 Reg7 Reg8 Reg9 Reg10 Reg11 Reg12 Reg13 Reg14 Reg15 Reg16 Reg17 Reg18 I Reg25 Reg26 Reg27 Reg28 Reg29 Reg30 Reg31 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 I 11001 11010 11011 11100 11101 11110 11111 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reserved Reserved HBD0 HBW0 VBW0 DA0b0 DA1b0 DA2b0 HBD1 HBW1 VBW1 DA0b1 DA1b1 DA2b1 HBD2 HBW2 VBW2 DA0b2 DA1b2 DA2b2 HBD3 HBW3 VBW3 DA0b3 DA1b3 DA2b3 HBD4 HBW4 VBW4 DA0b4 DA1b4 DA2b4 HBD5 HBW5 VBW5 DA0b5 DA1b5 DA2b5
MTV003N (MTV003)
HBD6 HBW6 x DA0b6 DA1b6 DA2b6
HBD7 HBW7 VBW7 DA0b7 DA1b7 DA2b7
Reserved
Reserved Reserved STF x RT0 x RT1 x Reserved STbsh Selft x x Reserved x x x x x x
1 1 1 1 1 1
XA0b0 XA1b0 XA2b0 XA3b0 XA4b0
XA0b1 XA1b1 XA2b1 XA3b1 XA4b1
XA0b2 XA1b2 XA2b2 XA3b2 XA4b2
XA0b3 XA1b3 XA2b3 XA3b3
XA0b4 XA1b4 XA2b4 XA3b4
XA0b5 XA1b5 XA2b5 XA3b5 XA4b5
XA0b6 XA1b6 XA2b6 XA3b6 XA4b5
XA0b7 XA1b7 XA2b7 XA3b7 XA4b7
XA4b3 XA4b4 Reserved
* The above x may represent any data. - Command Descriptions Reg0 (write) : Begins the H-Freq count. To read the value in the H-Freq registers, the write command (Reg0) needs to be issued first. : The status of polarity, presence and static level for HS and VS. 1. Hpol, Vpol = 1 -> positive, = 0 -> negative. 2. HSpre, VSpre, HVpre = 1 -> present, = 0 -> not present. 3. Hsl, Vsl = 1 -> high, = 0 -> low. * HVpre represents the status of the composite (H/V) presence in HS. Hsl or Vsl is valid only when HSpre or VSpre is not present. : Hfreq Count Finish flags, Hfreq high bit. 1. HCFF = 1 -> valid, 2. HF10 - HF8 = 3 high bit of Hfreq.
Reg0 (read)
Reg1 (read)
= 0 -> not valid.
Reg1 (write)
: Selects the source of VBLANK and controls the polarity status of Hpol, Vpol and SYNC output polarity. 1. HVcvs = 1 -> VBLANK is extracted from HS. = 0 -> VBLANK is extracted from VS. 2. HBpl = 1 -> negative HBLANK output, = 0 -> positive HBLANK output. 3. VBpl = 1 -> negative VBLANK output, = 0 -> positive VBLANK output. * After power-on, HBpl and VBpl shall be initialized to 0. 4. Hpf1, Hpf0 = 0,0 or 1,1 -> Hpol = x, by auto detection. = 0,1 -> force Hpol = 1. = 1,0 -> force Hpol = 0. 5. Vpf1, Vpf0 = 0,0 or 1,1 -> Vpol = x, by auto detection.
MTV003 Revision 2.3 07/01/1998 6/13
MYSON TECHNOLOGY
Reg 2 (read) Reg 2 (write) = 0,1 = 1,0 : H-Freq low byte. -> force Vpol -> force Vpol = 1. = 0.
MTV003N (MTV003)
: Begins V-Freq count. To read the value in V-Freq registers, the write command (Reg2) must be issued first. : V-Freq Count Finish flag, V-Freq high bit. 1. VCFF = 1 -> valid, = 0 -> not valid. 2. VF8 = the high bit of V-Freq. : Controls test and clock modes. 1. TEST =0 -> Normal mode. =1 -> Test mode, not allowed in applications. 2. CLK4M =0 -> CLK = X1 divided by 2 (for 8MHz crystal power-on [default]). =1 -> CLK = X1 (for 4MHz crystal power-on [default]). : V-Freq low byte. : Reserved. : Reserved. : Controls the delay of HBLANK output (7 bits). (HBD7 - 0) = 10000000 -> Directly bypasses Hsync to output. = 01000000 -> Min. propagation delay (approximately 300ns). = 00000000 -> T + 500ns. = 00000001 -> 2T + 500ns. = 00111111 -> 64T + 500ns. : Controls the width of HBLANK output (7 bits). (HBW7 - 0) = 10000000 -> Directly bypasses Hsync to output. = 01000000 -> Min. width (approximately 300ns). = 00000000 -> T + 500ns. = 00000001 -> 2T + 500ns. = 00111111 -> 64T + 500ns. : Reserved. : Controls the width of Vblank output (7 bits). (VBW7 - 0) = 1-000000 -> Directly bypasses Vsync to output. = 0-000000 -> Min. width (approximately 8us). = 0-000001 -> 16 + 8(us). = 0-111111 -> 16 * 63 + 8(us) = 1.016ms. : Output pulse width control for DA0. : Output pulse width control for DA1. : Output pulse width control for DA2. : Reserved.
MTV003 Revision 2.3 07/01/1998 7/13
Reg3 (read)
Reg3 (write)
Reg4 (read) Reg4 (write) Reg5 (write) Reg6 (write)
Reg7 (write)
Reg8 (write) Reg9 (write)
Reg10 (write) Reg11 (write) Reg12 (write) Reg13 (write)
MYSON TECHNOLOGY
Reg14 (write) Reg15 (write) Reg16 (write) : Reserved. : Reserved.
MTV003N (MTV003)
: Controls i) enabler, ii) band selection, iii) 4 pattern modes and iv) output enabler for the self-test pattern generator. 1. Selft =1 -> Enables generator. =0 -> Disables generator. 2. STbsh =1 -> 63.5KHz (horizontal) output selected. =0 -> 31.75 KHz (horizontal) output selected. 3. RT1, RT0 = 0,0 -> Positive cross-hatch pattern output. = 0,1 -> Negative cross-hatch pattern output. = 1,0 -> Full white pattern output. = 1,1 -> Full black pattern output. 4. STF= 1 -> Enables STOUT output. =0 -> Disables STOUT output. : Reinitializes all internal registers. : Output pulse width control for XDA0. : Output pulse width control for XDA1. : Output pulse width control for XDA2. : Output pulse width control for XDA3. : Output pulse width control for XDA4. : Reserved.
Reg17 (write) Reg26 (write) Reg27 (write) Reg28 (write) Reg29 (write) Reg30 (write) Reg31 (write)
*1. The above T = 250ns. 2. All D/A converters are centered with a value of DA7 - 0= 10000000, and other registers are initialized with low after power-on or a Reg17 write. 3. The duration of power-on initialization is 200ms and Reg17 write reinitiation is 2.5ms. No register access is allowed during initialization.
MTV003 Revision 2.3 07/01/1998 8/13
MYSON TECHNOLOGY
4.0 ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage (VDD) Voltage with respect to Ground: All pins except VDD and DA0 to DA2 DA0 to DA2 Storage Temperature Ambient Operating Temperature -0.3 to 7 V -0.3 to VDD+ 0.3 V -0.3 to +13.2 V -65 to +150 oC 0 to +70 oC
MTV003N (MTV003)
5.0 OPERATING CONDITIONS
DC Supply Voltage (VDD) External D/A Power Supply Operating Temperature +4.75 V to +5.25 V +5 V to 12 V 0 to +70 oC
6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions)
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage Conditions (Notes) Min. 2.4 (for all input pins) VSS-0.3 (for all input pins) IOH = -500 uA (for pins of HBLANK, 3.0 VBLANK, DIO, Bout, STOUT, XDA4-0) IOL = 4 mA (see VOH) IDAOL = 3 mA (for pins of DA2-0) (for pins of DA2-0, pulled up 5 by external 5 to 12V power supply) Vin = VDD, Iout = 0 uA. (all input pins connected to VDD, all output pins without connection) Max. VDD+ 0.3 0.8 Unit V V
VOH
Output High Voltage
-
V
VOL VDAOL VDAOH
Output Low Voltage Open-Drain D/A Output Low Voltage Open-Drain D/A Output High Voltage
0.5 0.35
V V
12
V
ICC
Maximum Quiescent Supply Current
20
mA
MTV003 Revision 2.3 07/01/1998 9/13
MYSON TECHNOLOGY
Symbol fDAO fXTAL fHS fVS tHIPW tVIPW Parameter D/A Converter Output Frequency Crystal Frequency HS Input Frequency VS Input Frequency HS Input Pulse Width VS Input Pulse Width HSYNC (Rise) to HBLANK Output Delay (programmed by Reg6) HSYNC (Rise) to HBLANK Output Delay (bypass HSYNC to HBLANK Output directly) HBLANK Output Width (programmed by Reg7) HBLANK Output Width (bypass HSYNC to HBLANK Output directly) HSYNC to HBLANK Output Jitter VBLANK Output Width (programmed by Reg9) VBLANK Output Width (bypass VSVNC to VBLANK Output directly) HSYNC to VBLANK Output Delay (H/V mode) VS to VBLANK Output Delay (H+V mode) VSYNC to VBLANK Output Jitter(H+V mode) HSYNC to VBLANK Output Jitter (H/V mode) CMDB to DCK Setup Time CMDB to DCK Hold Time DIO to DCK Setup Time (write) DIO to DCK Hold Time(write) DCK High Time DCK Low Time DCK to DIO Delay Time(read) Min. 15 20 0.5 25 300 Typ. 31.25 8 (N+1)xT+500 Max. 100 100 6.5 2000
MTV003N (MTV003)
7.0 SWITCHING CHARACTERISTICS (Under Operating Conditions and X1=8MHz)
Unit KHz MHz KHz Hz us us ns
64xT+850
tHHBD
-
-
50
ns
300 0.5 16 25
(N+1)xT+500 (Nx16)+8 -
64xT+850 7 (+/-) 25 1016 2000
ns us ns us us
tHBW
tHHBJ
tVBW
tHVBD tVVBD tVVBJ tHVBJ tCDSU tCDH tDDSU tDDH tDCKH tDCKL TDDD
200 100 200 100 200 200 100
1 H-line -
50 (+/-) 25 (+/-) 25 -
ns ns ns ns ns ns ns ns ns ns
* 1. The above HSYNC is extracted from HS input and VSYNC is extracted from VS, HS input. * 2. T = 250ns (1/4MHz) is fixed regardless of whether or not an 8(or 4)MHz crystal is used. * 3. 0 < N < 63
MTV003 Revision 2.3 07/01/1998 10/13
MYSON TECHNOLOGY
8.0 TIMING DIAGRAMS
MTV003N (MTV003)
MTV003 Revision 2.3 07/01/1998 11/13
MYSON TECHNOLOGY
MTV003N (MTV003)
Figure 6. 4 Self-Test Patterns
MTV003 Revision 2.3 07/01/1998 12/13
MYSON TECHNOLOGY
MTV003N (MTV003)
Figure 7. Self-Test Timing
MTV003 Revision 2.3 07/01/1998 13/13

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